RAG on Eric Hsiao | IC Design Engineer

RAG on Eric Hsiao | IC Design Engineerhttps://erichsiao1106.github.io/tags/rag/Recent content in RAG on Eric Hsiao | IC Design EngineerHugozh-twTue, 14 Apr 2026 00:00:00 +0000RTL-AI-Lab：用 Claude API 加速 IC 前端設計https://erichsiao1106.github.io/projects/rtl-ai-lab/Tue, 14 Apr 2026 00:00:00 +0000https://erichsiao1106.github.io/projects/rtl-ai-lab/8 天走完 IC 前端設計全流程，再用 Claude API 打造 EDA 工具鏈——Debug Agent、MCP Server、RAG 查詢、Spec 自動生成 RTL。準備 AI 工程師面試：API 整合和 Fine-tuning 我踩過的坑https://erichsiao1106.github.io/blog/ai-engineer-interview-prep/Tue, 14 Apr 2026 00:00:00 +0000https://erichsiao1106.github.io/blog/ai-engineer-interview-prep/從 Rate Limit 到 LoRA，從 Prompt Caching 到 Fine-tuning vs RAG 的選擇框架——這是我實際寫過程式之後整理的筆記，不是教科書。